Why a chip has that exact die area — the design SPEC question
Thoughts on chip specifications, yield and die-area trade-offs.
Adapted from my own Dimensity 8500 video script. The video is in progress.
Background data
| Chip | Length (mm) | Width (mm) | Area (mm²) |
|---|---|---|---|
| Dimensity 8500 (D8500) | 10.91 | 8.63 | 94.15 |
| Apple A18 Pro | 13.00 | 7.84 | 101.92 |
1. Defect density and yield
D0 stands for defect density.
Think of a TSMC wafer as a very expensive sheet of dough, with defects like grains of sand mixed into the flour. If a grain lands in a core, that core is lost.
Manufacturers often build in redundancy:
I make eight cores. As long as seven work, I can sell the chip as a “Dimensity 8400.” That is how an otherwise unusable chip gets a second chance.
So far, the logic seems reasonable: disabling a core on the 8400 might look like cutting the product down, but could actually be an expensive insurance policy against unstable yield.
But as a tech creator, I want to look at the numbers, not just the story.
The Dimensity 8400 uses TSMC N4. With D0 already below 0.05 at the time, the manufacturing-yield calculation gives:
- 696 complete dies per wafer
- 665 good dies, 31 defective dies and 77 unusable edge dies
- A yield of 95.51%
2. What does disabling a core recover?
Let’s use the Poisson distribution to work through the numbers. With a starting yield of 95.51%, how many chips does that extra redundant core actually recover?
Calculation: 13.12% × 31 = 4.067 dies
Note: An earlier calculation was incorrect and has been corrected. The disableable area is the total area of all disableable cores, not the area of one core.
That means roughly one out of every 165 Dimensity 8500 chips would have a defect in the GPU that forces it to be downgraded to an 8400.
The other 164 were already fully functional chips.
My reading of this is that it looks less like insurance against poor yield and more like deliberate product segmentation: holding back a fully enabled design for a year, then releasing it as an upgrade when competitors put on the pressure.
That brings us to another interesting number: die size.
| Chip | Area (mm²) | Relative to Dimensity 8200 |
|---|---|---|
| Dimensity 8500 | 94.15 | +10.85% |
| Snapdragon 8 Gen 5 | 103.55 | — |
| Snapdragon 8s Gen 4 | 105.56 | — |
Dimensity 8500 is about 9.07% smaller than Snapdragon 8 Gen 5 and almost 11% smaller than 8s Gen 4.
“We always talk about changes in chip area. Couldn’t the designer simply have drawn it a little bigger?“
3. Why choose that particular area?
Mask Field Utilization
In chip design, every bit of area matters.
Core count, IP layout, I/O and even the final die size are constraints set early in the SPEC definition. Why target 94.15 mm² in particular?
One manufacturing consideration is MFU: Mask Field Utilization.
The field exposed in a single lithography shot typically measures 26 mm × 33 mm. Think of it as a fixed frame: the designer wants to fit as many dies inside it as possible.
For example:
- A 13 mm × 16.5 mm die fits four times in one exposure field, with nearly perfect utilization.
- Increase the die to 13 mm × 17 mm, just 0.5 mm more in one dimension, and only two fit.
That increases the number of exposures needed per wafer and reduces throughput.
Using the Dimensity 8500 dimensions, 10.91 mm × 8.63 mm, in a 26 mm × 33 mm field gives:
MFU: 96.72%
The layout fits nine dies into each exposure field, using almost all of its area.
That raises another question:
“If the field is 26 mm × 33 mm, why not fill it with a 3 × 3 layout? Wouldn’t making each die 8.65 mm × 11 mm take MFU straight to 100%?”
Overall Wafer Effectiveness
It is not quite that simple. There is another factor: OWE, Overall Wafer Effectiveness.
Dies are rectangular, but wafers are round. This measure captures how effectively the full wafer area is used.
| Layout | Die dimensions | Wasted wafer area | Dies per wafer |
|---|---|---|---|
| Hypothetical “filled field” | 8.65 mm × 11 mm | 13.38% | 688 |
| Actual Dimensity 8500 dimensions | 10.91 mm × 8.63 mm | 13.25% | 696 |
The choice of die area therefore involves optimizing both MFU and OWE.
Throughput and contracts
Other designs make different trade-offs. Take Apple’s A18 Pro:
| Metric | Dimensity 8500 | A18 Pro |
|---|---|---|
| MFU | 96.72% | 75.23% |
| Wasted wafer area | 13.25% | 14.46% |
| Exposures per wafer | 131 | 115 |
MediaTek uses the available area very efficiently. Why would Apple accept a less area-efficient layout?
My interpretation is that Apple is trading expensive wafer area for more efficient production time.
The A18 Pro has a larger die. Its lower MFU may look wasteful, but the layout covers a wider footprint per shot. The scanner takes fewer steps across the wafer, reducing processing time per wafer.
For a premium product with high margins, the argument is that Apple can afford some wasted wafer area. Faster wafer turnaround could matter more when supporting the enormous volumes required for a global launch.
We can even speculate that Apple’s contract with TSMC might be priced per good die, with substantial penalties for late delivery. Under that kind of pressure, shortening production time could matter more than saving wafer area.
MediaTek’s Dimensity 8500 takes a different route. The upper-midrange market is intensely price-sensitive. To get those eight extra dies, MediaTek accepts 16 additional scanner steps. Even one dollar less in cost per chip can strengthen its negotiating position with phone manufacturers.
Closing thoughts
One approach prioritizes throughput and turnaround; the other prioritizes die output and cost. This is why defining a chip’s SPEC is complicated: many different numbers and constraints have to be considered together.